PACKET RADIO: IO Bus Information
(This text from the W8IZ packet radio bulletin
board. It's formatted to fit a 80 character screen.)
FOIL SIDE Rear Panel COMPONENT SIDE Ground B1 A1 ~I/O Check Reset (powerup) B2 A2 Data bit 7 +5 V DC B3 A3 Date bit 6 IRQ 2 B4 A4 Data bit 5 -5 V DC B5 A5 Data bit 4 D REQ 2 B6 A6 Data bit 3 -12 V DC B7 A7 Data bit 2 Reserved B8 A8 Data bit 1 +12 V DC B9 A9 Data bit 0 Ground B10 A10 I/O Channel Ready ~MEMW B11 A11 AEN ~MEMR B12 A12 Address bit 19 ~IOW B13 A13 Address bit 18 ~IOR B14 A14 Address bit 17 ~D ACK 3 B15 A15 Address bit 16 D REQ 3 B16 A16 Address bit 15 ~D ACK 1 B17 A17 Address bit 14 D REQ 1 B18 A18 Address bit 13 ~ D ACK 0 B19 A19 Address bit 12 Clock 4.77MHz B20 A20 Address bit 11 IRQ 7 B21 A21 Address bit 10 IRQ 6 B22 A22 Address bit 9 IRQ 5 B23 A23 Address bit 8 IRQ 4 B24 A24 Address bit 7 IRQ 3 B25 A25 Address bit 6 ~D ACK 2 B26 A26 Address bit 5 T/C B27 A27 Address bit 4 ALE B28 A28 Address bit 3 +5 V DC B29 A29 Address bit 2 OSC 14.31818MHz B30 A30 Address bit 1 Ground B31 A31 Address bit 0
ALE Address Latch Enable T/C Terminal Count (DMA) AEN Address Enable MEMR/W Memory Read/Write IOR/W IO Read/Write
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